ARCHITECTURE FOR AN aVLSI STEREO VISION SYSTEM
نویسندگان
چکیده
This paper introduces a depth-computation architecture designed for, but not limited to, a single-chip current mode analog VLSI (aVLSI) implementation of stereo vision. The architecture implements a modified version of the block matching algorithm; pixel blocks are averaged (summed) vertically before comparison along the horizontal axis. This both reduces the effects of noise and provides an order-of-magnitude reduction in computational complexity. Simulation results indicate performance on par with a full implementation of block matching.
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